The present invention relates to a regulator circuit for generating power supply voltage, and more particularly, to a circuit and method for reducing output noise generated when a pulse width modulation (PWM) mode is started.
In the prior art, DDC circuits (DC-DC converters) are known as regulator circuits. A DDC circuit typically includes either a PWM circuit or a pulse frequency modulation (PFM) circuit or includes both PWM and PFM circuits. The PWM circuit adjusts the pulse width of a pulse signal for driving an output transistor in accordance with an output voltage to maintain a constant power supply voltage, which is be supplied to a load. The PFM circuit selectively generates a pulse signal in accordance with the output voltage and adjusts the frequency of the pulse signal. Other examples of regulator circuits include linear regulators that linearly control an output voltage, such as low dropout (LDO) circuits. For example, Japanese Laid-Open Patent Publication Nos. 2005-198484 and 2005-130622 describe regulator circuits that include both linear regulators and switching regulators (DDC circuits).
FIG. 1 is a schematic block circuit diagram of a conventional regulator circuit (DDC circuit) 100 that includes a PWM circuit 102 and a PFM circuit 104.
The PWM circuit 102 includes an error amplifier 112 for generating a control voltage VER in accordance with the difference between an output voltage VO and a reference voltage VREF1. The error amplifier 112 is connected to a PWM generator 114. The PWM generator 114 compares a control voltage VER with a reference pulse wave (not shown) and generates a pulse signal SPWM having a variable duty cycle.
The PFM circuit 104 includes a comparator 116. The comparator 116 compares an output voltage VO with a reference pulse wave VREF2 and generates a comparison signal VCOMP. The comparator 116 is connected to a PFM generator 118. The PFM generator 118 selectively generates a pulse signal SPFM having a substantially constant duty cycle in accordance with the level of the comparison signal VCOMP, which is provided from the comparator 116.
The PWM circuit 102 and the PFM circuit 104 are connected to a multiplexer 120. The multiplexer 120 selects one of the pulse signal SPWM and the pulse signal SPFM as a drive pulse signal SDRV in response to a mode selection signal S1. A pre-driver 122 generates drive signals VH and VL for driving output transistors T1 and T2 in a complementary manner based on the drive pulse signal SDRV.
A first terminal of a coil L1 is connected to a node N1 between the output transistors T1 and T2. A capacitor C1 is connected between a second terminal of the coil L1 and ground. The capacitor C1 smoothes the output voltage VO generated at the second terminal of the coil L1.
When the output transistor T1 is activated and the output transistor T2 is deactivated, current corresponding to an input voltage VIN flows from the node N1 to the coil L1. This charges the coil L1 with energy (current). When the output transistor T1 is deactivated and the output transistor T2 is activated, the energy accumulated in the coil L1 is discharged via a loop formed by the output transistor T2, the coil L1, and the capacitor C1. Accordingly, the coil L1 accumulates energy, the amount of which corresponds to the duty cycle of the drive signal VH (or the drive signal VL). The output voltage VO is controlled in accordance with the amount of accumulated energy.
FIG. 2 is a schematic waveform chart showing a mode switching operation of the regulator circuit 100 of FIG. 1.
When the regulator circuit 100 is operating in a PFM mode, only the PFM circuit 104 is activated. In this mode, the multiplexer 120 selects the pulse signal SPFM as the drive signal SDRV. As a result, the transistors T1 and T2 are driven at a substantially constant duty cycle.
Subsequently, the PWM circuit 102 is activated (the PFM circuit 104 is deactivated) at timing t1. This switches the operation mode of the regulator circuit 100 from the PFM mode to the PWM mode. The multiplexer 120 selects the pulse signal SPFM as the drive signal SDRV in response to the mode selection signal S1.
The duty cycle of the pulse signal SPWM is not constant when the PWM circuit 102 starts operating. The error amplifier 112 of the PWM circuit 102 usually has an offset resulting from manufacturing variations. For example, the reference voltage VREF1 of the error amplifier 112 may be lower than its originally intended target value. In this case, the PWM circuit 102 generates a pulse signal SPWM that lowers the output voltage VO. More specifically, the drive signals VH and VL drive the output transistors T1 and T2 so as to discharge the energy accumulated in the coil L1. This results in the output voltage VO including an unintended noise (voltage drop).
FIG. 3 is a schematic block circuit diagram of a conventional regulator circuit 200 that includes a DDC circuit 202 and an LDO circuit 204.
The DDC circuit 202 includes a PWM circuit 210, a pre-driver 212, and an output circuit 214 (transistors T1 and T2). The PWM circuit 210 includes an error amplifier 216 and a PWM generator 218. The error amplifier 216 and the PWM generator 218 start operating in response to an enable signal DDCEN. The PWM circuit 210 receives an output voltage VO1 (VO) via a feedback loop FB1 to control the duty cycle of a pulse signal SPWM in accordance with the level of the received output voltage VO1. The PWM circuit 210 shown in FIG. 3 operates in the same manner as the PWM circuit 102 shown in FIG. 1. Thus, the operation of the PWM circuit 210 will not be described in detail.
The LDO circuit 204 includes an output transistor T3, resistors 222 and 224, and an error amplifier 226. The error amplifier 226 starts operating in response to an enable signal LDOEN. The output transistor T3 receives a control signal VLDO from the error amplifier 226 and generates an output voltage VO2 (VO) from an input voltage VIN in response to the received controlled voltage VLDO. The output voltage VO2 is supplied from a feedback loop FB2 to the error amplifier 226 as a feedback via a node N2 between the resistors 222 and 224. The error amplifier 226 compares a reference voltage VREF with the feedback voltage of the output voltage VO2. Based on the comparison result, the error amplifier 226 generates the control voltage VLDO to compensate for fluctuations in the output voltage VO2.
The regulator circuit 200 selectively operates the DDC circuit 202 (or the PWM circuit 210) and the LDO circuit 204 in accordance with the enable signals DDCEN and LDOEN and generates the output voltage VO in either the PWM mode or the LDO mode.
FIG. 4 is a schematic waveform chart showing a mode switching operation of the regulator circuit 200 of FIG. 3.
When the LDO circuit 204 is activated in the LDO mode based on a high (H) level enable signal LDOEN, the PWM circuit 210 is deactivated based on a low (L) level enable signal DDCEN. In this case, the regulator circuit 200 outputs the output voltage VO2 that is generated by the LDO circuit 204 as the output voltage VO.
Subsequently, the PWM circuit 210 starts operating in response to an H level enable signal DDCEN at timing t1. This switches the operation mode of the regulator circuit 200 from the LDO mode to the PWM mode.
When the PWM circuit 210 begins operating, the coil L1, which is connected to the node N1 of the DDC circuit 202, has not been charged with current energy. Further, the error amplifier 216 of the PWM circuit 102 has an offset in the same manner as the error amplifier shown in FIG. 1. Thus, the duty cycle of the pulse signal SPWM is lower than its expected value (the duty increases gradually from zero). As a result, the energy stored in the coil L1 and the offset of the error amplifier 216 may cause the output voltage VO to include unintended noise (voltage drop).